Digitalised technologies are an important building block in the conservation of resources and the improvement of energy efficiency in various different applications. However, processors, power electronics and data memories also require energy themselves to function. Although there aren’t any conclusive numbers as to how high the energy demand actually is, pessimistic estimates expect that, in ten to 20 years, information technology will account for up to 50 per cent of global electricity consumption.

That is why the semiconductor industry is working on ­continual improvements to the energy efficiency of its ­products: chip manufacturers are developing ever more energy-efficient CPUs (central processing units), and multi-core technology or the use of GPUs (graphics processing units) is making it possible to process higher loads with less power. Most CPUs also have power management features that optimise electricity consumption by dynamically switching between different power states depending on the workload. For example, with low-power chips, electricity consumption in standby mode is lower by a factor of one million than when they are active, i.e. when the chip processes data.

New chip architectures

Changing the basic architecture of a microchip can also help to considerably reduce its energy consumption. IBM, for example, has introduced a chip prototype whose design enables transistors to be stacked vertically. This means that, in addition to the ability to house more transistors on a chip, a greater electrical current from top to bottom is also enabled. This reduces loss of energy – the new chip is said to consume up to 85 per cent less energy with this configuration.

Another approach is so-called neuromorphic computing. The main aim of this technology is to process the enormous volume of data from big-data applications and artificial intelligence. The goal is to emulate the functionality of the most energy-efficient and flexible memory on Earth – the brain – and to enable a high degree of plasticity. This is why the Fraunhofer Institute for Photonic Microsystems is working on new, non-volatile memory technologies based on ferroelectric hafnium dioxide (HfO2) for analogue and digital neuromorphic circuits. Ferroelectric materials are characterised by a change in their polarity when an electric field is applied. After switching off the voltage, the state of the polarity remains. Similar to the human brain, the hardware architecture of the chips is structured such that information is already saved in the system and is non-volatile. A complicated data transfer between the processor and memory is not necessary; the thinking output is already performed in the chip. As a single non-volatile memory concept, ferroelectric memories are operated purely electro-statically. This makes them especially energy-saving, as only the capacitive currents have to be expended in order to write data. 

Integration of cooling into the chip

Another important factor for reducing energy demand in semiconductor products is the cooling: this is because every computing or switching process ­generates heat. So far, the heat has generally been dissipated from the microchips using heat sinks. Any heat-sensitive components are also often cooled using fans. This uses up additional energy. As components become increasingly smaller and more compact, it becomes more and more difficult to dissipate the heat. 

One idea is to integrate the cooling directly into the chip, using microfluidic cooling systems. For example, researchers at the POWERlab at the Institute of Electrical Engineering, École Polytechnique Fédérale de Lausanne (EPFL), have developed a process in which tiny channels for a liquid coolant are cut directly into the silicon wafers. Although this is still just a research approach, it could revolutionise the energy efficiency of chips: cooling currently accounts for more than 30 per cent of the total energy consumption of data centres, for example. Researchers expect that, with this approach, this number could be reduced to less than 0.01 per cent.

New materials

An important application area of semiconductors is power electronics. They are used to “convert” energy, for example to integrate renewable energies into electric grids, charge smartphones, or control drives in the manufacturing and process industry. However, with each of these conversion processes, a part of the electric energy is lost as heat. Innovative “wide bandgap” semiconductor materials, such as gallium nitride and silicon carbide, enable considerably higher switching frequencies and thus generate less lost heat than silicon-based components.

According to the Fraunhofer Institute for Silicon Technology, the new materials reduce energy losses by more than 45 per cent. Based on the entire power module market, this means potential energy savings of up to 100 terawatt hours in the EMEA (Europe, Middle East, Africa) economic area, and up to 25 terawatt hours in the USA by 2025. By way of comparison, that makes up around a fifth of the electrical energy that the whole of Germany requires in one year. 

The post Mission to reduce energy consumption of digitalisation appeared first on Future Markets Magazine.

The year 2022 marks a milestone in the history of digitalisation: for the first time, almost two thirds of global GDP is being generated digitally, as forecast by an IDC study. The fundamental basis for this are reliable, high-performance IT systems and infrastructures. Quantum computers are extremely powerful and are therefore perfectly suited to processing the growing data volumes from the economy and society. 

Many times the performance

Quantum computers are intended to outperform conventional computers many times over because they work completely differently. Instead of classic bits, which can assume the value of 0 or 1, they use so-called quantum bits, which can be 0 and 1 at the same time. “This gives them enormous potential for tackling problems which classic computers cannot solve. In particular, they are promising to be able to solve important problems in the fields of logistics and medicine development. They are a central, key technology of the 21st century,” says Prof Klaus Sengstock, Head of Group at the Institute of Laser Physics at Universität Hamburg – in the next five years, a functioning quantum optimiser is to be created as part of a research project at the university. There are different options for constructing qubits. Photons, ions or superconducting circuits can form the physical basis for such designs. 

The global competition for the most powerful quantum computer has long been in full swing, with the markets of the future at stake. Subsidies, research groups and leading companies are shaping the dawn of the quantum age. “In quantum computing, we have reached a degree of maturity where this technology no longer just belongs in the lab,” explains Dr Walter Riess, Head of the Science & Technology department at IBM Research in Zurich, which has been awarded two Nobel prizes. 

Quantum processors are becoming more suited to application

The first quantum processors are already on the market: in 2021 IBM presented a quantum processor with 127 qubits. The group is aiming to build a quantum processor with over 1,000 qubits by 2023. A processor from QuEra Computing has 256 qubits and it should soon be available to customers. QuEra is using research results about neutral atoms, developed at Harvard University and the Massachusetts Institute of Technology, as the basis of its scalable, programmable quantum computer solution. The hardware uses arrays of neutral atoms in which hundreds of atoms are cooled and then arranged in small vacuum chambers by laser fields. While the glass walls of the chambers are at room temperature, just millimetres away, the atoms are laser-cooled to one millionth of a degree Kelvin above absolute zero. That is more than a million times colder than space and over a thousand times colder than the superconducting qubits from other industry figures such as IBM and Google. “There is an enormous opportunity to make headway on some of today’s most critical – and presently impossible – problems that impact nearly every one of us,” said Alex Keesling, CEO of QuEra and co-inventor of QuEra’s technology. “With our first machine, we are excited to begin to demonstrate what quantum computers can do for humanity.” 

Qubits and semiconductors go hand in hand

According to Dell Technologies, in the future, quantum systems will not be standalone systems, but will work together closely with classic IT systems. This means QPUs (quantum processing units) will soon make their way into conventional systems and perform selected calculations there. Classic CPUs will take over the standard tasks and support the QPUs by preparing the data and evaluating the results.

Q.ant has developed a process, for example, that enables the electronic mainframe computers of today to be enhanced by processors which use state-of-the-art quantum technology. By applying highly specialised light channels to silicon chips, this photonic chip process allows quanta to be guided and controlled almost without any losses whatsoever, even at room temperature. 

Quantum effects can also improve semiconductor electronics directly, leading to a breakthrough when it comes to the bandwidth of data transfer, energy efficiency and information security. So-called heterostructures, i.e. layered systems made from superconducting and semiconducting materials, are promising successors to today’s semiconductor ­electronics. Two suitable materials in this regard are the superconductor niobium nitride (NbN), as well as the semiconductor gallium nitride (GaN). So far, it had been uncertain, however, as to how exactly the electrons on the contact surface of these two materials behave – and if the electrons from the semiconductor might possibly disrupt the superconduction, thereby cancelling out the quantum effects. Researchers at the Paul Scherrer Institute (PSI) investigated precisely these interactions but ultimately concluded in their experiments that the electrons in each material “keep to themselves”. Vladimir Strocov, researcher at the synchrotron Swiss Light Source SLS at the PSI: “This layer system could actually create a new form of semiconductor electronics which incorporates and uses the quantum effects in superconductors.” This could bring about a new turn in semiconductor technology and make electronic components much more powerful in the future. 

The post A quantum leap in semiconductor technology appeared first on Future Markets Magazine.

1 Moore’s Law still applies

The CMOS transistor density will continue to follow Moore’s Law over the next few years. This is primarily enabled by progress in EUV patterning and by the roll-out of innovative chip architectures. FinFET technology is reaching its limits with scaling over five nanometres. ­Nanosheet or gate-all-around transistors offer the solution: this is a modified transistor structure where the gate is in contact with the channel on all sides and enables continuous scaling. They promise power ­increases of more than 25 per cent and a reduction in electricity consumption by more than 50 per cent.

2 new chip architectures enter the market

The x86 architecture has dominated the ­microprocessor industry for over 50 years. However, this is now ­changing: the ARM architecture is increasingly ­impressing with its performance and low electricity consumption. ARM provides its IP to chip ­manufacturers; these manufacturers then develop their own chips based on this and can have them produced in foundries. ­Furthermore, the RISC-V architecture has gained importance in IoT devices and other applications due to the benefit of it being open source and its improved electricity consumption.

3 new materials to complement silicon

Silicon as a base material for microchips is increasingly reaching its limits. The demand for increasingly small and fast integrated circuits has pushed material ­efficiency to the limits of what is possible. Research into new materials is in progress – there are several future materials that are very promising. High-performance gallium nitride has been able to be used in power grids for more efficient and faster power conversion thanks to its high critical energy field. Semiconductors based on antimony and bismuth are used in improved infrared sensors for the medical and military field. Graphene has the potential to surpass silicon as an all-purpose semiconductor material – however, widespread ­commercialisation could still be up to twenty-five years away. Pyrite could be used as a substitute for the rare earth element cadmium telluride, which is in ­widespread use in solar cells, but is limited in supply. Pyrite is ­abundant, cheap and non-toxic.

4 artificial intelligence has the edge

With an expected growth of significantly over 100 per cent in the next five years, edge AI is one of the biggest trends in the chip industry. The application of learnt ­“knowledge” (the inference) is embedded in the endpoints of the ­Internet of Things in edge AI. Commercially available edge AI chips now provide efficiency in the order of 1 to 100 tera operations per second per watt (TOPS/W). Fast GPUs or ASICs are used for the calculations here. Significantly higher levels of efficiency are required in order to implement the IoT. Research is being carried out into solutions that achieve an efficiency of 10,000 TOPS/W 

5 new 3D technologies enable ­hetero­geneous integration

Heterogeneous integration, i.e. integration of various types of electronic components on a chip will be increasingly important in the future in order to overcome the memory limit or to increase the functionality in systems with a limited form factor. 3D integration technologies form the basis for this. Distances of approximately 30 micrometres can currently be realised between the junctions, the solder balls or microbumps in production. The aim is to further reduce these distances. For ­example, IMEC has already achieved junction ­distances of seven micrometres. These kinds of high-density ­junctions in the case of heterogeneous integration enable a 3D junction density between the chips that is more than 16 times greater; this means that the space ­required is significantly reduced.

6 nonvolatile memories on the rise

The speed of scaling is noticeably decreasing in the case of nonvolatile memories. Yet, processes such as ­wafer-to-wafer bonding in the case of NAND memories or EUV lithography in the case of DRAMs still offer potential for improvement in terms of patterning, but they are starting to approach their limits. In contrast, new approaches promise further improvement in ­storage capacity. This includes magnetoresistive random-­access memory (MRAM), which enables significantly ­faster memory access while still offering a lower energy ­consumption than electronic memories such as DRAMs at the same time. Additionally, MRAM memory cells on a chip only require a fraction of the space that DRAM or SRAM cells take up, for example. 

7 increasing logic performance

Transistors will continue to shrink in the future – but the increase in performance with the same power consumption has slowed down significantly. One reason for this is the required scaling of the current and voltage supplies, as electrical connections are minimised with the patterns – this increases their resistance. The buried power rails (BPR) in the substrate could be a solution for this: they are intended to enable an increase in power at the system level thanks to optimised power distribution. ­Furthermore, research is being carried out into new materials that reduce resistance: these include hybrid metallisation with ruthenium or molybdenum. In the future, interconnects on the chips could consist of binary alloys and cobalt-based materials instead of copper; these are then intended to reduce line resistance.

8 CMOS and MEMS join forces

Established CMOS technologies will increasingly be supplemented with MEMS (micro-electromechanical systems) in the future. The CMOS wafers serve as an ­“intelligent” substrate here, as they already contain control and readout circuits, signal processing and interfaces for energy transmission. Through the combination of CMOS and MEMS, inexpensive and extremely compact micro-systems for use in areas including medicine, ­industry, mobility and aerospace can be created. 

The post 8 trends that will shape the future of the semiconductor industry appeared first on Future Markets Magazine.

Whether it’s lasers, screens, computers or optical storage solutions – they all rely on components that combine optics with semiconductor electronics. Nowadays, the technology for generating, recording and controlling light – ­optoelectronics – is used in a wide variety of applications. The most obvious optoelectronic components are doubtless light-emitting diodes (LED). Thanks to their energy efficiency, they aren’t just a popular solution for lighting systems in buildings, they can also be found in high-resolution displays on smartphones, in TV sets, in vehicle lighting systems, in the telecommunications industry and in industrial production processes. An LED is a semiconductor device that emits light when an electric current flows through it. 

Although the biggest leaps in the development of LED technology have already been made, there is still potential for innovation in this field. For example, chemists from the University of Jena have discovered a fluorescent aluminium complex with the highest quantum yield known to date: for virtually every photon absorbed by the substance, a photon is emitted. This could be of benefit in applications such as LED technology. “The record so far for aluminium complexes is around 70 per cent,” explains Robert Kretschmer, Junior Professor for Inorganic Chemistry of Catalysis at Friedrich Schiller University Jena. “This means that with this quantum yield, for every ten light particles absorbed, seven new ones are emitted by the substance. In our complex, however, almost every light particle is converted into a new one.” 

Disinfection using light

During the Covid-19 pandemic, one particular use case for LED technology attracted particular attention: LEDs that emit ultraviolet (UV) radiation can be used to disinfect surfaces, air and water quickly, in an eco-friendly way, without chemicals. For example, the Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik (FBH) has developed UV-LED-based radiation systems that will in future be able to inactivate multi-resistant pathogens such as MRSA and coronaviruses like SARS-CoV-2 directly on humans with no harmful effect on the skin. Each system is equipped with 120 LEDs that emit light at a wavelength of 233 nanometres. Thanks to optimised semiconductor epitaxy and chip process technology, these new-generation LEDs can be operated with currents that are twice as high as before – they provide more than 3 milliwatts of output power at 200 milliamperes.

A new technology for displays

Miniaturisation is also all the rage in the field of optoelectronics – just look at micro-LEDs, for example. They measure less than 50 micrometres and require much less space to generate pixels. According to market analysts from MarketsAndMarkets, the market for micro-LEDs is set to reach 21,169 million US dollars in 2027 – equivalent to annual growth of 81.5 per cent between 2021 and 2027.

Full-colour micro-displays can be created by combining red, green and blue (RGB) micro-LEDs. Compared with current display technology, micro-LEDs provide a greater pixel density, a longer service life, increased brightness, a higher switching speed and a wider colour spectrum. What’s more, micro-LEDs also stand out from the pack with their very low energy consumption – making them ideal for future generations of small mobile devices where space for batteries is at a premium.

Like conventional LEDs, micro-LEDs are also manufactured using the MOCVD (metal organic chemical vapour deposition) method, where the semiconductors are applied to the substrate material, atomic layer by atomic layer, each just one atom thick. However, the requirements for the production process are much higher. 

Light from silicon

Despite the aforementioned progress, the ultimate challenge in the field of optoelectronics is finding a way to combine silicon and photonics directly. If this were achieved, future microchips would be able to transmit signals and information not by current, but instead by light pulses – which do not generate any waste heat and would enable much faster data transfers. As a result, researchers have been working for 50 years on building light-emitting components from silicon or germanium. Their efforts have, so far, been unsuccessful. Silicon, the workhorse of the chip industry, normally crystallises in a cubic crystal lattice. In this form, it is unsuitable for converting electrons into light.

However, researchers at Eindhoven University of Technology have now managed to develop alloys made of germanium and silicon capable of emitting light. The crucial step was to produce germanium and alloys made from germanium and silicon with a hexagonal crystal lattice. “This material has a direct band gap, and can therefore emit light itself,” says Prof. Jonathan Finley, Professor of Semiconductor Nanostructures and Quantum Systems at the Technical University of Munich. “If we can implement on-chip and inter-chip electronic communications by optical means, speeds can be increased by a factor of up to 1000,” says Finley. “In addition, the direct combination of optics and electronics could drastically reduce the cost of chips for laser-based radar in self-driving cars, chemical sensors for medical diagnostics, and air and food quality measurements.” 

The post Let there be light appeared first on Future Markets Magazine.

Technological advancements in the semiconductor industry have led to a drastic fall in the costs per transistor: whilst they were around 1,000 cents in the 1960s, costs fell to below 0.000020 cents at the turn of the millennium. There are many reasons for this. Firstly, continuous advancements in production processes meant that the integrated circuits could be made smaller, allowing for ever-more chips to be produced from a wafer. At the same time, the wafers themselves became bigger, again enabling more chips to be produced per wafer. Secondly, the rising demand for microchips automatically led to lower unit costs. According to an article in the journal “Proceedings of the IEEE”, the costs per transistor fell by a factor of around two each time the transistor volume produced doubled – or put another way, the average annual cost reduction rate for transistors was previously in the order of 35 per cent per year.

Production processes are becoming more complex

Nevertheless, these relationships are now changing, caused by the ongoing focus on miniaturising components down to 7, 5 or 2 nanometres patterns. Whilst it is true that this means further improvements to the transistor density (meaning Moore’s law is likely to continue to apply for many years to come), this will only be ­possible through complex technical measures – with a corresponding ­increase in production costs. At its investor conference back in 2020, Marvell – a fabless manufacturer of memory, telecommunications and semiconductor products – presented a diagram showing that the price per 100 ­million gates continued to fall (to 1.30 US dollars) until the roll-out of the 28 nanometres node. Since then, the price has risen again – for a 7 nanometres node it is back up to 1.52 US dollars. This reversal in the trend can be seen when moving from the 28 nanometres to the 20 nanometres node, and is due to the fact that the 28 nanometres node was one of the last “planar” nodes, i.e. with a two-dimensional surface. ­FinFET technology with its three-dimensional patterns was introduced thereafter – it is much more complex and requires additional production steps. Handel Jones, CEO of International Business Strategy Corporation (IBS), said: “The average cost of designing a 28 nanometres chip is 40 million US dollars. By comparison, the cost of designing a 7 nanometres chip is 217 million US dollars and the cost of designing a 5 nanometres device is 416 million US dollars. A 3 nanometres design will cost up to 590 million US dollars.”

Twice as many production steps

The latest developments such as chiplets and advanced packaging technologies promise to reduce development and manufacturing costs. The long-term average costs per processed silicon wafer surface are also only increasing slowly – in part thanks to the roll-out of larger wafer diameters. However, anyone wanting to use future high-end chips with 5 or 2 nanometres designs will have to accept higher costs. According to CMC Materials, a supplier of critical materials to semiconductor manufacturers, one reason for this is that a 5 nanometres node requires twice as many production steps as a 10 nanometres node. For example, more cleaning is required. For a 5 nanometres node, the number of cleaning steps alone makes up around 30 per cent of all production steps, as this is the only way to comply with the stringent quality and cleanliness requirements. 

Rising equipment prices

The second major driver of rising costs are the tools and manufacturing plant and equipment required. “Chip manufacturing with EUV helps reduce the amount of critical lithography masks (-40 per cent) and process steps (-30 per cent) when compared to non-EUV manufacturing. This results in significant defect, cost and cycle time reductions for our customers,” reports ­Martin van den Brink, President, Chief Technology Officer and Vice Chair of the Management Board at ASML. EUV ­lithography ­systems like this currently already cost more than 100 million US dollars. However, the new 5 or 2 nanometres nodes will ­require a leap in technological progress – for example, the new-generation EUV platform from ASML will enable 60 per cent smaller features and increase microchip density by a factor of almost 3 times. Nevertheless, according to various media reports, the price of a system like this is likely to exceed 300 million US dollars.

This means that chip manufacturers will need to signi­ficantly increase the volume of semiconductor products they produce in order to offset the higher development and equipment costs. A good thing, then, that the ­demand for chips shows no signs of abating, and that digital ­processes and workflows are becoming ever-more widespread. 

The post Reversing the trend appeared first on Future Markets Magazine.

Reliability means that the microchip performs its tasks throughout its entire service life without any faults. Up to now, the semiconductor industry has concentrated on quality control during the production process, followed by a test of the finished chip – but this only ensures a product that is manufactured without fault, not its reliability in the field over the longer term. In the consumer industry, where high-end chips with feature sizes of 10 nanometres or smaller are above all used, this is not yet such a big problem. Here, it has so far generally been permitted for one in a million chips to fail within an assumed service life of two years. However, since more and more high-end chips are also being used in safety-critical applications, they must become more reliable. The automotive industry, for example, is demanding that chips can function for 18 years without fault, or that only one chip per billion fails in this time. The requirements are becoming more stringent in other markets, too. Smartphone manufacturers are also now specifying that chips have to work for four years, rather than the two years previously. And in certain industrial and IoT applications where replacing sensors is difficult, chips also sometimes have to last 20 years or longer. 

Increasing reliability

In order to increase the reliability of a microchip, the designers must have an overview of the interaction between all of the components. The circuit board, joining technology and chip housing must be perfectly designed, taking into account the environmental conditions of where it will be used in the future, too. Moisture can also lead to corrosion in the chip and vibration can cause connections to loosen, etc.

Furthermore, the reliability of the actual semiconductor device must be considered. There are some rough guidelines here: chips made of relatively coarse patterns tend to be less susceptible to influences such as cosmic radiation or fluctuating operating voltages. In contrast, chips with a smaller area suffer less from mechanical stress factors such as vibration or differences in temperature. Chips are also subject to an ageing process. Electron migration causes discontinuity in conductor strips, and effects from temperature, such as bias temperature instability (BTI) and hot carrier injection (HCI), play an ever-greater role in highly integrated chips. The terms ageing, wear or degradation are used here. Due to the continuing miniaturisation of microelectronic components, these negative changes to the material properties have become even more varied and complicated. Locally occurring current densities and field intensities within a circuit tend to reach critical values in smaller patterns, for example.

In standard electronics, designers usually minimise the risk of failure by integrating a safety reserve in their designs. This “over design” is, however, expensive, time consuming and is no longer feasible with technologies that are becoming smaller and smaller.

Chips with integrated self-test

One solution to at least detect pending failures at an earlier stage is to integrate self-tests into the chip. With so-called built-in self tests (BIST), integrated circuits are enhanced by hardware or software functions which they can use to test if they are working. The processor clock can be monitored, for example, by a “clock control” detecting any clock errors. And if the worst comes to the worst, the system is automatically placed in a safe state and an applicable signal generated.

Predicting failures

There are solutions that go one step further by monitoring the entire chip and using artificial intelligence to signal when a failure is about to occur. Israeli company proteanTecs has, for example, developed an on-chip monitoring method. It links a software platform based on machine learning with specifically developed agents. These are already integrated into the semiconductor design during the development stage and work as sensors in the semiconductor. When they are read out and the data obtained is analysed, it is possible to gain an insight into the functionality and performance capability of semiconductors and electronic systems. Especially when it comes to new semiconductor generations, these results can be used to improve quality and reliability and extend the service life.

Simulating ageing

To avoid an “over design”, designers can also integrate a simulation of the expected ageing into the IC development process. This means the reliability of the designs can be precisely predicted as early as the design stage. For example, the Fraunhofer IIS is developing approaches for this at its Division Engineering of Adaptive Systems EAS in Dresden. Under the slogan “Physics-of-Failure”, they are linking knowledge about the physical mechanisms with approaches based on statistical data regarding failures during use. This means that, in the future, electronics design teams can efficiently assess potential reliability issues with semiconductors and systems – and do this before they are manufactured.

Fingerprint for electronics

Trustworthiness is a topic that is closely related to reliability. This is because counterfeit chips or chips that have been tampered with can also cause failure during use. Researchers at Ulm University are therefore working on developing a forgery-proof physical “fingerprint” for electronic circuit boards, programmable circuits and integrated circuits (FPGA and microcontrollers). The idea is based on there being unavoidable process fluctuations during the production of the components, which causes the smallest deviations on a nanolevel. By recording these deviations in detail, it becomes possible to identify the component over its entire service life. This means that it is always possible at a later stage to find out whether a component is an original or whether it has been modified to the detriment of the application. The idea behind this is that uniquely identifying electronic components is the key to greater reliability. 

The post Just one in a billion appeared first on Future Markets Magazine.

The term packaging has a completely different meaning in electronics to everyday life. When we talk about packaging in conjunction with semiconductors, we mean the development and manufacture of housings for integrated circuits. Packaging is an important part of semiconductor manufacture and development because it affects the electricity consumption, performance and costs, as well as the fundamental functionality of a chip.

The original task of a semiconductor housing is to protect the integrated circuits (IC) from environmental influences and prevent physical damage or corrosion on the silicon elements, logic units or memories. The packaging is also needed to be able to mount the chip on a circuit board, and the housing is used to make the electrical connections. In applications that use a lot of power, the heat generated by the silicon chip is also dissipated via the housing using a heat sink. Chip housings can be made from plastic, glass or metallic materials, too. 

More and more pins, increasingly smaller

Since the first semiconductor housing was developed in the 1960s, packaging technology has developed rapidly. There were two main aims here: integrating an ever-greater number of pins (i.e. connections) whilst simultaneously further reducing the area required. The first “real” chip package is considered to be a 14-lead ceramic dual in-line package (DIP) with two rows of pins that was developed by the three Fairchild engineers Don Forbes, Rex Rice and Bryant Rogers. Mass production of DIP housings started in the early 1970s.

The number of ICs and functions integrated in the chips increased rapidly at the start of the 1980s. The first chips with a million logic elements were launched on the market – they therefore had a correspondingly high number of connection points that the packaging technology had to meet. Consequently, so-called PGA (pin grid array) and BGA (ball grid array) packaging was introduced. These technologies allow considerably more pins per integrated circuit than older housings, such as the DIP.

Not much larger than the chip itself

The 1990s saw the advance of mobile devices. Laptops and mobile phones needed chip packaging that was as small as possible. There was a problem, however, as the chips up to that point had to be attached to a substrate using wire bonding. Here, the wires were fixed to the edges of the chips, meaning that you could only use as many wires as would fit around the chip. The wires were also relatively long, leading to a propagation delay and increased energy consumption. Flip-chip packaging was developed to get around this problem. Here, the wires are replaced by “bumps”, i.e. connection points on the entire surface of the IC or die. 

This meant CSPs (chip scale packages) could be developed. This is an umbrella term for different technologies in which the packaging dimensions are almost the size of an unpackaged chip, the so-called die. An example of this is the quad-flat no-leads package (QFN), in which the electrical connections (pins) do not extend out beyond the dimensions of the plastic casing at the sides but instead are integrated flat into the underneath of the housing. Due to its simplicity, performance and price, the QFN packaging is one of the most successful types. 

WLCSP (wafer-level chip-scale package) technology enables the smallest packaging currently available. In contrast to BGA or flip-chip packaging, which all have either a metal or organic substrate as an intermediate layer, the chip is connected directly to the circuit board with WLCSP. Only the solder balls and often a thin polymer layer separate the silicon chip from the final circuit board assembly.

More and more functions on a chip

Mobile digitalisation and the Internet of Things are continuing to drive miniaturisation. Electronics must be more highly integrated at ever-lower costs and produced to a high quality. Advanced packaging provides a response to these challenges: bare dies or flip-chips are integrated with other components to make ultra-compact systems in a package (system-in-package – SiP). Here, stacking chips is a possible option to obtain even lower electricity consumption, a smaller form factor, higher performance and greater function density – resulting in three-dimensional chips. Through-silicon vias (TSVs) are a key technology in this regard. These are direct vertical connections between the different levels of a stacked chip. 

But with more and more functions in a holistic design, the production processes are becoming more and more complex, and therefore also more prone to errors. As a consequence, the production output is lower and the costs increase. The optimal size of the pattern is also not the same for each function module. One solution is provided by chiplets. Here, an individual chip is divided into small chips that work together in an optimised package. This splitting-up of the monolithic design can more than double the output. Furthermore, different functional units can thus be produced with several photolithographic processes, each with the optimum pattern size. Several chiplets working together in a single integrated circuit is called a multi-chip module (MCM). 

On course to the Ångström Era

Development is also continuing within advanced packaging technologies, too. New processes are still making it possible to increase the number of transistors per component. Intel’s packaging roadmap, for example, aims to increase the performance-per-watt ratio each year by ten to twenty per cent. Progress is then to continued to completely new dimensions below the nanometre range – which Intel is calling the Ångström Era. An ångström is a unit of measurement measuring 0.1 of a nanometre. The company is aiming to launch chips in this magnitude on the market from 2024.

So, looking at the packaging technologies, it can be said that Moore’s law will still apply for many years. Thanks to innovative production and packaging technologies, the possibilities are not yet exhausted. 

The post It’s all about packaging appeared first on Future Markets Magazine.

For over 50 years, the semiconductor industry has kept pace with Moore’s Law, doubling the density of transistors in an integrated circuit about every two years. This has been possible in particular due to the continual progress in microlithography. The wavelength of the light sources used in the lithography system has become ever shorter, making it possible to transfer increasingly smaller patterns onto the wafers. At first, the wavelengths were 436 nanometres in size, but with ongoing technological development reduced to 405, 365, 248 and 193 nanometres until they reached 13.5 nanometres: this is called EUV lithography. 

Ultra-fine patterns with UV light

EUV stands for “extreme ultraviolet” – i.e. light with an extremely short wavelength. Microchips manufactured using EUV lithography have been in mass production since the end of 2018. With this technology, it is now possible to produce chips with patterns as small as seven or even five nanometres. But the development hasn’t stopped there: as well as the wavelength, the so-called “numerical aperture” is crucial to the size of the patterns on a chip. The value delineates the brightness and resolution of an optical system. The greater the numerical aperture, the better a lens can resolve details. Thanks to ever more precise manufacturing technologies, EUV lithography systems of the latest generation can reach a numerical aperture of 0.55. This enables the production of ICs as small as two nanometres – the most technologically sophisticated ICs in the world. 

The next generation is already waiting

The development process is far from over: global lithography research is already focussing on ways to further miniaturise the patterns. The term “next generation lithography” is used to refer to a range of successor technologies to conventional photolithography. This includes x-ray lithography and processes such as electron beam lithography and ion beam lithography.

When using x-ray lithography with wavelengths of 0.4 to 4 nanometres, it is theoretically possible to produce smaller patterns – with the process boasting a considerably greater depth of field. Instead of chrome-coated glass masks, films made of beryllium, and sometimes silicon, are used. To enable the x-ray beams to be absorbed, the films are coated with heavy elements, such as gold. Both the systems and the masks are very expensive. Nevertheless, according to market analysts from Fact.MR, due to the demand for ever smaller chips, the global market for x-ray lithography systems is set to continue growing by an average annual rate of 4.3 per cent up to 2031.

In electron beam lithography (EBL), the pattern is transferred onto the photoresist using a focussed electron beam with a spot size in the nanometre range. The resolution is not limited by the wavelength of the electrons: at 20 kiloelectron volts, it is only around nine picometres. But in practice, the size of the pattern is limited by the electron optics, the spread of the electrons in the exposed sample and the properties of the resist. Although the procedure is slow in terms of production process, it offers a high level of accuracy and flexibility. Furthermore, it eliminates the need for masks, which helps to reduce costs. 

Another possibility of lithography is exposing the wafers using ions. With the ions, it is possible to apply patterns to the wafer via a mask, or write on the wafer directly like in the electron beam method. In the case of hydrogen ions, the wavelength is 0.0001 nanometres.

Patterns that assemble themselves

An entirely different way of creating patterns on a wafer is “Directed self-assembly” (DSA). In DSA, different materials are used – especially so-called “block copolymers” (BCP), which consist of two continuous strands of different polymers that are connected to each other and are just a few tenths of a nanometre long. These two polymer chains repel each other, similar to oil and water. The similar components try to stay together, while simultaneously the opposing components try to separate from one another. That is why they move around until they form a nanoscale pattern. By adjusting the volume of the blocks in the polymer chain, it is possible to generate a series of different regular patterns and shapes. However, the self-assembly capability of these patterns is only one milestone on the path towards establishing actual manufacturing processes. They have to be positioned where the transistors in the integrated circuit are required. This can be achieved by using traditional lithography methods to generate guide patterns. These channel the block copolymers such that they create nanoscale properties on the surface of a silicon wafer. With the first of these materials, it was only possible to create reliably functioning semiconductors in the 22-nanometre range. But with recent materials, it has been possible – at least in the lab – to ­realise processes for semiconductor patterns as small as five nanometres.

Will Moore’s Law no longer apply?

Despite the ongoing claim since 2010 that Moore’s Law has reached its limits and further miniaturisation of chips is no longer possible, experts now expect that the law will continue to apply for at least another ten years. Currently, high-end chips have pattern sizes of five nanometres. However, both Intel and TSMC are already planning the series production of two-nanometre chips – meaning that up to 50 billion transistors can be built into a chip the size of a fingernail. Having more transistors in a chip also means more possibilities of integrating, for example, computing power for AI applications and new means of hardware-supported security and encryption into the chip. Furthermore, two-nanometre chips are said to be 45 per cent more powerful/consume 75 per cent less energy than seven-nanometre nodes. We could be seeing this high-tech wonder on the market from 2025.

But the belief is that, even with these chips, Moore’s Law still won’t end there: in future, new packaging technologies, innovative materials and complex 3D designs will further increase the number of transistors per component. Intel has set itself the goal of creating a chip with a trillion transistors by 2030. 

The post Moore’s Law ­has by no means reached the end appeared first on Future Markets Magazine.

Ever since semiconductor technology has been around, customer requirements have generally not changed much – microchips should be ever better, faster and cheaper. And the semiconductor industry has indeed made great advances in the development of its semiconductor products. It has consistently continued implementing Moore’s law, according to which the number of ICs on a microchip doubles every two years. Smaller chips with densely packed transistors enable smaller, more powerful electronic devices to be produced at lower prices. A comparison often cited in the industry illustrates this progress very clearly: if the automotive industry had achieved similar performance improvements in the last 30 years, then a Rolls-Royce would cost just 40 dollars and be able to travel round the earth eight times with one gallon of petrol – with a top speed of 2.4 million miles per hour. 

More Moore or More Than Moore?

The development of semiconductors is increasingly coming up against the limits of Moore’s law. Nowadays, the patterns on the chips are getting close to an atomic scale and cannot be reduced further. One solution is a 3D approach. Here, layers of transistors are stacked on top of each other. This means the number of components per square millimetre can be further increased, even if the physical area dimensions cannot be reduced any more. Manufacturers could also layer different semiconductor materials over each other in the process, for example, by applying a layer made from compound semiconductors such as indium gallium arsenide on a layer with conventional silicon transistors. They can assume special tasks such as particularly fast signal enhancement or detecting light. Many experts see an alternative continuation of Moore’s law in integrating additional functions in the chips in this way. Instead of “More Moore” (further miniaturisation), their motto is rather “More than Moore” (combining digital and non-digital functions on the same chip). These types of solutions can already be found today in many components, such as in microelectromechanical systems (MEMS) or in radio frequency and analog/mixed-signal technologies (RF/AMS).

New solutions for AI applications 

Many innovations in the semiconductor industry have been started by two higher-level technological trends: artificial ­intelligence and the Internet of Things.

AI is posing completely new challenges for semiconductor technology as the data volumes processed and stored in the process are huge. Improved semiconductor architecture is required to manage these. This process is less about improving the overall performance or computing power, but more about accelerating the data transfer out of and into the memory, as well as more efficient memory systems. Because of this, special neural chips have been developed which work like the synapses of the human brain. Instead of constantly sending signals, they only work when required. Furthermore, AI chips process data in numerous parallel processes, not in a sequence like previous processors. Alongside this, nonvolatile memories are increasingly being used in AI semi­conductors. They can also store data without a constant power supply. Combining these nonvolatile memories with AI processors on a “system-on-a-chip” provides a solution for the requirements posed by modern AI applications.

Microchips in the Internet of Things

The Internet of Things is based on small-scale microprocessors built into various objects and which communicate wirelessly. Integrated sensors enable these mini-computers to detect and monitor their environment, process the data they capture, and share it with other objects or the Internet.

This requires microcontrollers which integrate sensors, processors, memories, Wi-Fi capability, microelectromechanical systems and a range of analog and digital circuits on a limited space. At the same time, the electricity consumption should be as low as possible as the (mostly mobile) objects cannot be connected to an electricity grid or it would be too expensive and time consuming to replace the battery frequently. For example, at the moment, there are considerations about replacing the base material silicon, which is generally used in integrated circuits today, with a new semiconductor material such as gallium arsenide.

As many IoT devices must also withstand harsh environmental conditions, there are high requirements in terms of the robustness of the semiconductor products, for example when it comes to resistance to vibration, temperature, water and/or salt.

High performance for 5G 

The IoT will only be able to realise its full potential with the new mobile radio standard 5G, however. With a high bandwidth and transmission quality, along with low latency, in many areas 5G is the technical basis for the next step in the development of the IoT. Here, a solution is provided by radio frequency and power electronics based on gallium nitride (GaN) or silicon carbide (SiC). These so-called wide-bandgap semiconductors (WBG) are characterised by considerably higher energy efficiency, for example.

Energy-efficient power electronics 

WBG semiconductors for power electronics can be manufactured ten times smaller than conventional silicon semiconductors, and they lose up to 50 per cent less heat. Furthermore, transistors made from WBG semiconductors can increase the switching frequency compared to silicon transistors by up to 500 per cent. Thanks to these properties, SiC and GaN semiconductors can meet increasing customer ­requirements in many applications – from electromobility to photovoltaic inverters, right up to fast chargers. 

The post Smaller, more powerful, more cost-effective appeared first on Future Markets Magazine.

The European Union believes strengthening semiconductor expertise in Europe is an investment in a key future technology and an important step for maintaining and expanding its competitiveness. It has therefore invested billions into this endeavour in the form of the “European Chips Act” and the development programme “Important Project of Common European Interest” (IPCEI). In the current discussion, it often appears as if Europe were more or less a desert when it comes to the semiconductor industry. Nevertheless, almost ten per cent of all semiconductors globally are, in fact, produced in Europe. Over the past few years, we have seen the formation of clusters all focussed on semiconductor technology. These are regional hubs where different actors in the semiconductor industry have taken up residence. Eleven of these cluster regions alone have joined forces to form Silicon Europe – representing around 2,000 cluster members from science and industry.

Chips and more from Saxony

The largest micro-electronics site in Europe ist “Silicon Saxony”, which has the four semiconductor fabs Globalfoundries, Infineon, Bosch and X-Fab near Dresden as its key companies. According to the association, every third chip produced in Europe now bears the imprint “Made in Saxony”. A large number of companies from various areas of the semiconductor industry have come together around the fabs – around 2,500 Saxony-based companies with 70,500 employees are active across all stages of the value chain. They also benefit from the highly academic environment in this free state: four universities, five technical colleges, nine Fraunhofer institutes, three Leibniz institutes, one Helmholtz institute and two Max-Planck institutes are active in the field of micro-electronics/information and telecommunications technology – and often even world-leading. This makes “Silicon Saxony” Europe’s largest micro-electronics location and the fifth-largest in the world. So much expertise and development attracts additional investment, as Harald Kröger, Member of the Board of Management at Robert Bosch GmbH, explained: “In Dresden, modern entrepreneurship meets scientific excellence and industrial-political responsibility,” said Kröger. “Bosch has therefore made the conscious decision to make the largest single investment in its more than 130-year history here in the region.” In 2021, the company’s new semiconductor factory in Dresden went into operation; the new site produces semiconductors on the basis of 300-millimetre technology for the growing number of applications in mobility and the Internet of Things.

Highlands of micro-electronics

In 2021, Infineon also opened its new high-tech chip ­factory for power electronics on 300-millimetre thin ­wafers, but chose Villach in Austria for its site. With this investment, the “Silicon Alps Cluster” experienced considerable momentum. AT&S and AVL – who are active in mobile energy supply – have also invested substantial sums here. “Networks and clusters are the foundation for innovation, economic success and the competitiveness of regions and companies,” said Dr Robert Gfrerer, CEO of the Silicon Alps Cluster GmbH. The Silicon Alps Cluster is a fast-growing network of companies, organisations and research institutions, dedicated to the development of the electronic and micro-electronic sector in the south of ­Austria. 

Chips from the Emerald Isle

Ireland is another of the key semiconductor production centres in the EU, and it has been operating in the semiconductor space for several decades: in 1976, Analog Devices opened a factory in Limerick, and the opening of Intel’s European production and technology hub near Dublin in 1989 saw the industry become firmly established on the Emerald Isle. One reason for this is bound to be that the Irish tax system has been especially competitive for a long time. Since then, Ireland has also seen the formation of an industry-led cluster, MIDAS, which consists of around 70 industrial companies, educational and research institutions and government agencies. The members operate across the entire spectrum of the micro and nano-electronics industry in Ireland – design, consultation, technology, research and manufacturing. 

A sector of significance

These days, the European semiconductor eco-system provides around 200,000 direct and up to 1,000,000 induced jobs in systems, applications and services in Europe. According to the European Semiconductor Industry Association (ESIA), overall, micro and nano-electronics help to generate at least ten per cent of GDP in Europe – which demonstrates another success of the strong semiconductor clusters. “Collaboration between industry and governments is of vital importance for further success,” said Kurt Sievers, President of the European Semiconductor Industry Association (ESIA). 

The post Strength in unity appeared first on Future Markets Magazine.