It’s all about packaging

In the first 40 years of chip ­development, it was the production technology that was above all responsible for the great progress in line with Moore’s law. Today, packaging technology is just as important for continuing to increase the number of transistors per component.

The term packaging has a completely different meaning in electronics to everyday life. When we talk about packaging in conjunction with semiconductors, we mean the development and manufacture of housings for integrated circuits. Packaging is an important part of semiconductor manufacture and development because it affects the electricity consumption, performance and costs, as well as the fundamental functionality of a chip.

The original task of a semiconductor housing is to protect the integrated circuits (IC) from environmental influences and prevent physical damage or corrosion on the silicon elements, logic units or memories. The packaging is also needed to be able to mount the chip on a circuit board, and the housing is used to make the electrical connections. In applications that use a lot of power, the heat generated by the silicon chip is also dissipated via the housing using a heat sink. Chip housings can be made from plastic, glass or metallic materials, too. 

More and more pins, increasingly smaller

Since the first semiconductor housing was developed in the 1960s, packaging technology has developed rapidly. There were two main aims here: integrating an ever-greater number of pins (i.e. connections) whilst simultaneously further reducing the area required. The first “real” chip package is considered to be a 14-lead ceramic dual in-line package (DIP) with two rows of pins that was developed by the three Fairchild engineers Don Forbes, Rex Rice and Bryant Rogers. Mass production of DIP housings started in the early 1970s.

The number of ICs and functions integrated in the chips increased rapidly at the start of the 1980s. The first chips with a million logic elements were launched on the market – they therefore had a correspondingly high number of connection points that the packaging technology had to meet. Consequently, so-called PGA (pin grid array) and BGA (ball grid array) packaging was introduced. These technologies allow considerably more pins per integrated circuit than older housings, such as the DIP.

Not much larger than the chip itself

The 1990s saw the advance of mobile devices. Laptops and mobile phones needed chip packaging that was as small as possible. There was a problem, however, as the chips up to that point had to be attached to a substrate using wire bonding. Here, the wires were fixed to the edges of the chips, meaning that you could only use as many wires as would fit around the chip. The wires were also relatively long, leading to a propagation delay and increased energy consumption. Flip-chip packaging was developed to get around this problem. Here, the wires are replaced by “bumps”, i.e. connection points on the entire surface of the IC or die. 

This meant CSPs (chip scale packages) could be developed. This is an umbrella term for different technologies in which the packaging dimensions are almost the size of an unpackaged chip, the so-called die. An example of this is the quad-flat no-leads package (QFN), in which the electrical connections (pins) do not extend out beyond the dimensions of the plastic casing at the sides but instead are integrated flat into the underneath of the housing. Due to its simplicity, performance and price, the QFN packaging is one of the most successful types. 

WLCSP (wafer-level chip-scale package) technology enables the smallest packaging currently available. In contrast to BGA or flip-chip packaging, which all have either a metal or organic substrate as an intermediate layer, the chip is connected directly to the circuit board with WLCSP. Only the solder balls and often a thin polymer layer separate the silicon chip from the final circuit board assembly.

More and more functions on a chip

Mobile digitalisation and the Internet of Things are continuing to drive miniaturisation. Electronics must be more highly integrated at ever-lower costs and produced to a high quality. Advanced packaging provides a response to these challenges: bare dies or flip-chips are integrated with other components to make ultra-compact systems in a package (system-in-package – SiP). Here, stacking chips is a possible option to obtain even lower electricity consumption, a smaller form factor, higher performance and greater function density – resulting in three-dimensional chips. Through-silicon vias (TSVs) are a key technology in this regard. These are direct vertical connections between the different levels of a stacked chip. 

But with more and more functions in a holistic design, the production processes are becoming more and more complex, and therefore also more prone to errors. As a consequence, the production output is lower and the costs increase. The optimal size of the pattern is also not the same for each function module. One solution is provided by chiplets. Here, an individual chip is divided into small chips that work together in an optimised package. This splitting-up of the monolithic design can more than double the output. Furthermore, different functional units can thus be produced with several photolithographic processes, each with the optimum pattern size. Several chiplets working together in a single integrated circuit is called a multi-chip module (MCM). 

On course to the Ångström Era

Development is also continuing within advanced packaging technologies, too. New processes are still making it possible to increase the number of transistors per component. Intel’s packaging roadmap, for example, aims to increase the performance-per-watt ratio each year by ten to twenty per cent. Progress is then to continued to completely new dimensions below the nanometre range – which Intel is calling the Ångström Era. An ångström is a unit of measurement measuring 0.1 of a nanometre. The company is aiming to launch chips in this magnitude on the market from 2024.

So, looking at the packaging technologies, it can be said that Moore’s law will still apply for many years. Thanks to innovative production and packaging technologies, the possibilities are not yet exhausted.