Reversing the trend

The semiconductor industry has been able to drastically reduce the price of microchips since the first ­semiconductor products came onto the market. However, the roll-out of ever-smaller chip patterns has put a stop to this trend, with the price per transistor now rising again.

Technological advancements in the semiconductor industry have led to a drastic fall in the costs per transistor: whilst they were around 1,000 cents in the 1960s, costs fell to below 0.000020 cents at the turn of the millennium. There are many reasons for this. Firstly, continuous advancements in production processes meant that the integrated circuits could be made smaller, allowing for ever-more chips to be produced from a wafer. At the same time, the wafers themselves became bigger, again enabling more chips to be produced per wafer. Secondly, the rising demand for microchips automatically led to lower unit costs. According to an article in the journal “Proceedings of the IEEE”, the costs per transistor fell by a factor of around two each time the transistor volume produced doubled – or put another way, the average annual cost reduction rate for transistors was previously in the order of 35 per cent per year.

Production processes are becoming more complex

Nevertheless, these relationships are now changing, caused by the ongoing focus on miniaturising components down to 7, 5 or 2 nanometres patterns. Whilst it is true that this means further improvements to the transistor density (meaning Moore’s law is likely to continue to apply for many years to come), this will only be ­possible through complex technical measures – with a corresponding ­increase in production costs. At its investor conference back in 2020, Marvell – a fabless manufacturer of memory, telecommunications and semiconductor products – presented a diagram showing that the price per 100 ­million gates continued to fall (to 1.30 US dollars) until the roll-out of the 28 nanometres node. Since then, the price has risen again – for a 7 nanometres node it is back up to 1.52 US dollars. This reversal in the trend can be seen when moving from the 28 nanometres to the 20 nanometres node, and is due to the fact that the 28 nanometres node was one of the last “planar” nodes, i.e. with a two-dimensional surface. ­FinFET technology with its three-dimensional patterns was introduced thereafter – it is much more complex and requires additional production steps. Handel Jones, CEO of International Business Strategy Corporation (IBS), said: “The average cost of designing a 28 nanometres chip is 40 million US dollars. By comparison, the cost of designing a 7 nanometres chip is 217 million US dollars and the cost of designing a 5 nanometres device is 416 million US dollars. A 3 nanometres design will cost up to 590 million US dollars.”

Twice as many production steps

The latest developments such as chiplets and advanced packaging technologies promise to reduce development and manufacturing costs. The long-term average costs per processed silicon wafer surface are also only increasing slowly – in part thanks to the roll-out of larger wafer diameters. However, anyone wanting to use future high-end chips with 5 or 2 nanometres designs will have to accept higher costs. According to CMC Materials, a supplier of critical materials to semiconductor manufacturers, one reason for this is that a 5 nanometres node requires twice as many production steps as a 10 nanometres node. For example, more cleaning is required. For a 5 nanometres node, the number of cleaning steps alone makes up around 30 per cent of all production steps, as this is the only way to comply with the stringent quality and cleanliness requirements. 

Rising equipment prices

The second major driver of rising costs are the tools and manufacturing plant and equipment required. “Chip manufacturing with EUV helps reduce the amount of critical lithography masks (-40 per cent) and process steps (-30 per cent) when compared to non-EUV manufacturing. This results in significant defect, cost and cycle time reductions for our customers,” reports ­Martin van den Brink, President, Chief Technology Officer and Vice Chair of the Management Board at ASML. EUV ­lithography ­systems like this currently already cost more than 100 million US dollars. However, the new 5 or 2 nanometres nodes will ­require a leap in technological progress – for example, the new-generation EUV platform from ASML will enable 60 per cent smaller features and increase microchip density by a factor of almost 3 times. Nevertheless, according to various media reports, the price of a system like this is likely to exceed 300 million US dollars.

This means that chip manufacturers will need to signi­ficantly increase the volume of semiconductor products they produce in order to offset the higher development and equipment costs. A good thing, then, that the ­demand for chips shows no signs of abating, and that digital ­processes and workflows are becoming ever-more widespread.