For over 50 years, Moore’s Law has been applicable to the development of microchips. These are now so small that further miniaturisation hardly seems possible. But the development is far from reaching the end point.
For over 50 years, the semiconductor industry has kept pace with Moore’s Law, doubling the density of transistors in an integrated circuit about every two years. This has been possible in particular due to the continual progress in microlithography. The wavelength of the light sources used in the lithography system has become ever shorter, making it possible to transfer increasingly smaller patterns onto the wafers. At first, the wavelengths were 436 nanometres in size, but with ongoing technological development reduced to 405, 365, 248 and 193 nanometres until they reached 13.5 nanometres: this is called EUV lithography.
Ultra-fine patterns with UV light
EUV stands for “extreme ultraviolet” – i.e. light with an extremely short wavelength. Microchips manufactured using EUV lithography have been in mass production since the end of 2018. With this technology, it is now possible to produce chips with patterns as small as seven or even five nanometres. But the development hasn’t stopped there: as well as the wavelength, the so-called “numerical aperture” is crucial to the size of the patterns on a chip. The value delineates the brightness and resolution of an optical system. The greater the numerical aperture, the better a lens can resolve details. Thanks to ever more precise manufacturing technologies, EUV lithography systems of the latest generation can reach a numerical aperture of 0.55. This enables the production of ICs as small as two nanometres – the most technologically sophisticated ICs in the world.
The next generation is already waiting
The development process is far from over: global lithography research is already focussing on ways to further miniaturise the patterns. The term “next generation lithography” is used to refer to a range of successor technologies to conventional photolithography. This includes x-ray lithography and processes such as electron beam lithography and ion beam lithography.
When using x-ray lithography with wavelengths of 0.4 to 4 nanometres, it is theoretically possible to produce smaller patterns – with the process boasting a considerably greater depth of field. Instead of chrome-coated glass masks, films made of beryllium, and sometimes silicon, are used. To enable the x-ray beams to be absorbed, the films are coated with heavy elements, such as gold. Both the systems and the masks are very expensive. Nevertheless, according to market analysts from Fact.MR, due to the demand for ever smaller chips, the global market for x-ray lithography systems is set to continue growing by an average annual rate of 4.3 per cent up to 2031.
In electron beam lithography (EBL), the pattern is transferred onto the photoresist using a focussed electron beam with a spot size in the nanometre range. The resolution is not limited by the wavelength of the electrons: at 20 kiloelectron volts, it is only around nine picometres. But in practice, the size of the pattern is limited by the electron optics, the spread of the electrons in the exposed sample and the properties of the resist. Although the procedure is slow in terms of production process, it offers a high level of accuracy and flexibility. Furthermore, it eliminates the need for masks, which helps to reduce costs.
Another possibility of lithography is exposing the wafers using ions. With the ions, it is possible to apply patterns to the wafer via a mask, or write on the wafer directly like in the electron beam method. In the case of hydrogen ions, the wavelength is 0.0001 nanometres.
Patterns that assemble themselves
An entirely different way of creating patterns on a wafer is “Directed self-assembly” (DSA). In DSA, different materials are used – especially so-called “block copolymers” (BCP), which consist of two continuous strands of different polymers that are connected to each other and are just a few tenths of a nanometre long. These two polymer chains repel each other, similar to oil and water. The similar components try to stay together, while simultaneously the opposing components try to separate from one another. That is why they move around until they form a nanoscale pattern. By adjusting the volume of the blocks in the polymer chain, it is possible to generate a series of different regular patterns and shapes. However, the self-assembly capability of these patterns is only one milestone on the path towards establishing actual manufacturing processes. They have to be positioned where the transistors in the integrated circuit are required. This can be achieved by using traditional lithography methods to generate guide patterns. These channel the block copolymers such that they create nanoscale properties on the surface of a silicon wafer. With the first of these materials, it was only possible to create reliably functioning semiconductors in the 22-nanometre range. But with recent materials, it has been possible – at least in the lab – to realise processes for semiconductor patterns as small as five nanometres.
Will Moore’s Law no longer apply?
Despite the ongoing claim since 2010 that Moore’s Law has reached its limits and further miniaturisation of chips is no longer possible, experts now expect that the law will continue to apply for at least another ten years. Currently, high-end chips have pattern sizes of five nanometres. However, both Intel and TSMC are already planning the series production of two-nanometre chips – meaning that up to 50 billion transistors can be built into a chip the size of a fingernail. Having more transistors in a chip also means more possibilities of integrating, for example, computing power for AI applications and new means of hardware-supported security and encryption into the chip. Furthermore, two-nanometre chips are said to be 45 per cent more powerful/consume 75 per cent less energy than seven-nanometre nodes. We could be seeing this high-tech wonder on the market from 2025.
But the belief is that, even with these chips, Moore’s Law still won’t end there: in future, new packaging technologies, innovative materials and complex 3D designs will further increase the number of transistors per component. Intel has set itself the goal of creating a chip with a trillion transistors by 2030.